The present invention relates in general to the field of simulating and verifying the logical correctness of a digital circuit design on a register-transfer level and in particular to verifying a register-transfer level, design of an execution unit.
Modern execution units have a complex structure and implement a very large instruction set. For example, floating-point units (FPUs) of IBM system z9 and z10 implement more then 330 instructions with 21 different instruction formats and over ten different precisions. To ensure maximum reliability of such execution units, verification has to cover as much of the relevant state space as possible.
Typically, simulation is used to verify sequences of instructions executed in a model simulation environment. To make full use of the limited time available, realistic and interesting test cases as well as high simulation performance are essential. However, current simulation methods lack at least one of these characteristics.
Generally, there are the following existing approaches so the simulation of an execution unit. A first approach is test case generation using random number generators. A simple program generates input vectors that are then simulated in a simulation environment with a software-based model simulator. However this creates no realistic test scenarios, uses no knowledge about data formats, architecture, etc and only low simulation performance can be achieved.
A second approach is test case generation using architecture test case generators. A sophisticated program implemented in a high-level programming language such as C/C++ generates test cases that take into account all necessary aspects of the underlying processor architecture. The resulting test cases are then simulated in a simulation environment, with a software-based model simulator. However the test case generation is slow and also only low simulation performance can be achieved.
In the Patent Application Publication US 2009/0070717 A1 “Method and system for generation coverage data for a switch frequency of HDL or VHDL signals” by Deutschle et al a method and system for generating coverage data for a switch frequency of HDL or VHDL signals is disclosed. The disclosed method and system for generating coverage data for a switch frequency of HDL or VHDL signals are using a filtering algorithm or filtering rules for signals occurring in the HDL or VHDL hardware description model that is present at the register-transfer level. The method for generating coverage data for a switch frequency of hardware description language (HDL) signals, comprises the steps of providing a HDL hardware description model, within a register transfer level, providing a filtering algorithm for signals occurring in the HDL hardware description model, extracting signals from the HDL hardware description model, according to the filtering algorithm in order to get relevant signals, performing a simulation process on a compiled representation of the HDL hardware description model, performing a checking routine for the relevant signals in every cycle and storing the relevant signals in a data base.
Usually, the drivers, monitors, and checkers of the simulation environments are also written in high-level programming languages and thus are separate from the simulation model. This degrades simulation performance even further.
Using so-called hardware accelerators (e.g., AWAN machines) instead of software-based model simulators would improve the simulation performance drastically. However, this approach does not work well with the existing software-based test case generators and separate drives, monitors, and checkers. The simulation process would be slowed down and any potential performance benefit would be negated.